Independent Component Analysis (ICA) is a dimensionality reduction techniquethat can boost efficiency of machine learning models that deal with probabilitydensity functions, e.g. Bayesian neural networks. Algorithms that implementadaptive ICA converge slower than their nonadaptive counterparts, however, theyare capable of tracking changes in underlying distributions of input features.This intrinsically slow convergence of adaptive methods combined with existinghardware implementations that operate at very low clock frequencies necessitatefundamental improvements in both algorithm and hardware design. This paperpresents an algorithm that allows efficient hardware implementation of ICA.Compared to previous work, our FPGA implementation of adaptive ICA improvesclock frequency by at least one order of magnitude and throughput by at leasttwo orders of magnitude. Our proposed algorithm is not limited to ICA and canbe used in various machine learning problems that use stochastic gradientdescent optimization.
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